Circuit arrangement for power factor correction

ABSTRACT

Power factor correction circuit includes an input having a first and second connecting terminal, a first switching element with a control electrode coupled to a current source, a reference electrode coupled to a reference potential and a working electrode, an inductive resistor coupled between the working electrode of the first switching element and the first connecting terminal. The circuit also includes an output having a first and second output terminal, a first diode coupled between the working electrode and the first terminal of the output, a second switching element with a control electrode, a reference electrode coupled to the reference potential and a working electrode, a first capacitor coupled between the control electrode of the second switching element and the working electrode of the first switching element, and a first ohmic resistance coupled between the first connecting terminal of the output and the control electrode of the second switching element.

TECHNICAL FIELD

The present invention relates to a circuit arrangement for power factorcorrection.

Power factor correction serves the purpose of reducing the harmoniccontent of the input current of a circuit arrangement. Depending on thepower consumption of such a circuit arrangement, specific requirementsapply in this case. The requirements for ballasts having a powerconsumption of more than 25 W are outlined, for example, in the standardEN 61000-3-2, Part A 14.

PRIOR ART

A circuit known from the prior art for power factor correction isdescribed in DE 199 23 238.5.

Further circuit arrangements known from the prior art for power factorcorrection serve the purpose of driving a boost converter havingintegrated circuits, of driving a boost converter at a fixed frequencyin intermittent operation using discrete components or of using a chargepump in the resonant circuit of a downstream converter without using anupstream converter for power factor correction.

The disadvantage of the circuit arrangements known from the prior artfor power factor correction by means of a charge pump in the resonantcircuit consists in the fact that they result, in particular in the caseof electronic ballasts having higher ratings, in high wattless currentsin the load circuit. The disadvantage of the arrangement known from theprior art using fixed-frequency driving in intermittent operation is theunfavorable noise spectrum according to EN 55015.

The object of the present invention is therefore to provide a circuitarrangement for power factor correction which does not have thesedisadvantages and, moreover, can be realized cost-effectively.

SUMMARY OF THE INVENTION

This object is achieved according to the invention by a circuitarrangement for power factor correction having the features of patentclaim 1.

The invention is based on the knowledge that the above-described objectcan be achieved by a design using a self-oscillating boost converter incontinuous operation. Power factor correction is achieved by means ofthe constant On time of the central switching element in the transitionmode of operation. The constant On time and identification of thecurrent zero crossing in the inductance as is required for operation inthe transition mode is realized with minimum use of components. Theprovision of the first capacitor between the working electrode of thefirst switching element and the control electrode of the secondswitching element results in both the constant On time and in the firstswitching element being switched off in the zero crossing of the currentin the inductance. At the same time, the first capacitor performspositive feedback in the switching phases and thus reduces the switchinglosses owing to steep switching edges.

The solution according to the invention also has the advantage that, asa result of the continuous operation and the resulting frequencymodulation by the input voltage, the requirements placed on thecomponents, including an upstream EMC filter, are minimized. If thecircuit arrangement according to the invention is used for operating alamp, in particular in interaction with a cold-start electronic ballast,the high lamp impedance during the glow phase in the circuit arrangementaccording to the invention does not result in a severe increase in theintermediate circuit voltage as would be the case, however, with pumpcircuits known from the prior art.

The current source, to which the control electrode of the firstswitching element is coupled, is preferably realized either by a secondnonreactive resistor, which is coupled to the first connection terminalof the input and/or output, or by a separate low-voltage source having aseries resistor.

A limiter network, for example realized by means of a first zener diode,is preferably connected in parallel with the first nonreactive resistorand/or the second switching element such that it can be used to limitthe output voltage. This measure takes into account the fact that, inthe case of the circuit arrangement according to the invention, duringload shedding, for example during the starting phase or when removing aconnected lamp during operation, the output voltage rises inverselyproportional to the load. The parallel circuit comprising a first zenerdiode and the first nonreactive resistor prevents this by the inputpower being controlled downward when the zener voltage of this firstzener diode is reached, to such an extent that the output voltage of thecircuit arrangement cannot exceed the zener voltage. As an alternativeto this, the output voltage can be limited using a limiter network inparallel with the second switching element or oscillation can becompletely prevented when an output threshold voltage is reached.

The first switching element may comprise an nmos transistor, and/or thesecond switching element may comprise an npn transistor. Alternatively,the first switching element may comprise a pmos transistor, and/or thesecond switching element may comprise a pnp transistor.

The circuit arrangement is preferably designed such that, during a zerocrossing of the current through the inductance, the first switchingelement opens. This measure prescribes a simple condition for startingan oscillation. The zero crossing of the charge current, which flowsthrough the inductance and the first diode into the load circuit whenthe input voltage is applied, thus causes the circuit to start tooscillate.

A third nonreactive resistor is preferably coupled between the controlelectrode of the second switching element and the first connectionterminal of the input. This additional path increases the length of theOn time in the region of the zero crossing of the input voltage, whichhas an advantageous effect on the harmonic content of the input current.

The series circuit comprising a second diode and a second zener diodecan preferably also be coupled between the control electrode and thereference electrode of the second switching element such that the secondzener diode limits the voltage between the control electrode and thereference electrode of the second switching element in the reversedirection. The second diode prevents a current from flowing in thedirection forward of the second zener diode. The reverse voltage of thezener diode critically determines the duration of the On time of thefirst switching element and thus, at a given load, the level of theoutput voltage. If the two diodes are dispensed with, the reversevoltage is determined by the negative breakdown voltage of the junctionbetween the control electrode and the reference electrode of the secondswitching element.

Furthermore, the control electrode of the first switching element andthe working electrode of the second switching element is preferablycoupled to the reference potential by means of a third zener diode, thethird zener diode being arranged such that it can be used to protect thecontrol electrode of the first switching element against overvoltages.

Further advantageous embodiments are described in the subclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will now be explained in moredetail below with reference to the attached drawings, in which:

FIG. 1 shows a circuit diagram of a first embodiment of a circuitarrangement according to the invention;

FIG. 2 shows a circuit diagram of a second embodiment of a circuitarrangement according to the invention;

FIG. 3 shows a schematic illustration of the time characteristics ofvarious signals in FIGS. 1 and 2;

FIG. 4 shows the measured time characteristic of three signals of arealized exemplary embodiment;

FIG. 5 shows the time characteristic, associated with FIG. 4, of theinput current i_(e); and

FIG. 6 shows a circuit diagram of a third embodiment of a circuitarrangement according to the invention.

Identical elements and elements having identical functions in thevarious exemplary embodiments are given identical reference numeralsthroughout in the text which follows.

PREFERRED EMBODIMENTS OF THE INVENTION

Reference will first be made to the circuit arrangement according to theinvention which is illustrated in FIG. 1. Without restricting thepossible applications for the circuit arrangement according to theinvention, it will be described below using the example of anarrangement for driving an electronic ballast for a lamp. Theassociated, basic signal characteristics can be seen in FIG. 3.

A voltage u_(e) is made available to the circuit arrangement 12according to the invention by a voltage source, in particular a systemvoltage source. Firstly, it supplies a current i_(e) to a rectifiernetwork 10, which comprises four diodes D11, D12, D13, D14. The voltageu_(g) which is made available at the output of the rectifier network 10is stabilized by a capacitor C_(e) and supplied to the circuitarrangement 12 according to the invention for power factor correction.

The capacitor C₁ shall be charged at time t₀ to the negativebase/emitter breakdown voltage of the transistor Q₂. The transistor Q₂is thus in the off state, and the transistor Q₁ is in the on state via apull-up resistor R₁, i.e. the voltage u₁ across the drain terminal ofthe transistor Q₁ is zero. The current i₁ through the inductance L₁shall likewise be equal to zero at time t₀. The output voltage u_(z)across the load R_(L) shall be constant, for example with the aid of asufficiently large bulk capacitor C_(B).

The capacitor C₁ is now recharged via R₂ during the time T₁=t₁−t₀, T₁being given bydu _(C1) /T ₁=1/C ₁*(u _(z) /R ₂).  (1)

During the time period T₁, the current i₁ in the inductance L₁ riseslinearly. The gradient of the current ramp is given byi _(1,max) /T ₁=1/L ₁ *u _(g,)  (2)in which u_(g) is the input voltage of the circuit arrangement accordingto the invention.

At time t₁, the voltage u_(base) of transistor Q₂ reaches the forwardvoltage and switches the transistor Q₂ on. The voltage u_(gate) oftransistor Q₁ thus becomes zero, and the transistor T₁, for example aMOSFET here, turns off. At time t₁, the current i₁ through theinductance L₁ first commutates onto the capacitor C₁ and recharges saidcapacitor C₁ to the output voltage u_(z). Then, the current i₁commutates onto the rectifier diode D₁ and is thus supplied to theoutput circuit. Up to time t₂, the current i₁ in the inductance L₁decreases linearly. The gradient of the negative current ramp can becalculated fromi _(1,max) /T ₂=1/L ₁*(u _(g) −u _(z)),  (3)in which, disregarding an On time for the transistor T1, the followingequation applies: T₂=t₂−t₁. At time t₂, the current zero crossing in thediode D₁ is reached, see FIG. 3 b), and the diode D₁ turns off. Thecapacitor C₁ is discharged by means of the inductance L₁ and in thismanner depletes the base of the transistor Q₂. The transistor Q₂ thusturns off, and the voltage u_(gate) across the gate of the transistor Q₁is pulled up by means of the pull-up resistor R₁. Q₁ thus turns on andpulls the voltage u₁ across its drain to zero. The capacitor C₁ isdischarged by means of the drain/source junction of the transistor Q₁ upto the negative base/emitter breakdown voltage of the transistor Q₂.This positive feedback makes it possible for the transistor Q₁ to switchoff rapidly, and thus minimizes the switching losses. The state at timet₀ is thus reached, and the cycle begins from the beginning.

The circuit arrangement according to the invention provides for the timeT₁=t₁−t₀ to be constant independently of the input voltage u_(g) andthus independently of the voltage u_(e). It can be seen directly fromequation (2) that in this case i_(1,max) is proportional to the inputvoltage u_(g). Furthermore, the rms value of the current i₁ is equal tothe active component of the input current i_(g). In continuousoperation, the peak value for the current i₁ in the inductance L₁ isproportional to the input current i_(g) according to the equationi _(1,max)=√{square root over (3)}*i _(g)  (4)

The circuit principle in which the transistor Q₁ is opened again at thezero crossing of the current i₁ at time t₂ prescribes continuousoperation. The condition for power factor correction is as follows:u_(e)˜i_(e)  (5)and, from (3) and (4) where u_(g)=|u_(e)| and i_(g)=|i_(e)|, is thus metby the circuit arrangement according to the invention.

To start the oscillation:

Once a voltage u_(g) has been applied, the capacitor C₁ is charged bymeans of the inductance L₁ and the diode D₁. The base of the transistorQ₂ is driven via the resistor R₂ whilst the output voltage u_(z) isbuilt up, as a result of which the transistor Q₂ turns on. The voltageu_(gate) across the gate of the transistor Q₁ is thus equal to zero andin this phase turns the transistor Q₁ off.

Once the capacitor C₁ has been recharged when the first voltage peakvalue for the input voltage has been reached, the current i₁ through theinductance L₁ passes through zero. As has already been explained above,this results in the capacitor C₁ being recharged and a cycle starting,as shown in FIG. 3. The circuit arrangement according to the inventionthus begins to oscillate automatically once the input voltage has beenapplied.

With reference to the embodiment illustrated in FIG. 2 of a circuitarrangement according to the invention, further refinements of thecircuit principle according to the invention are described below: thetime T₂ decreases inversely proportionally to the increasing outputvoltage u_(z). The input power is thus pulled back as the output voltageu_(z) increases, which is advantageous for the circuit arrangement. Inorder to completely adjust the output voltage u_(z) in the case of aresistive load, the input power would need, however, to be pulled backin proportion to the square of the output voltage u_(z). This means thatthe output voltage u_(z) during load shedding, for example during thestarting phase of a lamp or when removing a lamp during operation,nevertheless increases inversely proportionally to the load. In order toprevent this, a zener diode D₄ can be introduced. Said zener diode D₄ isin parallel with the nonreactive resistor R₂ and limits the outputvoltage u_(z) by the time T₁ and thus the input power being controlleddownward when the zener voltage across the zener diode D₄ is reached, tosuch an extent that the output voltage u_(z) cannot exceed the zenervoltage of the diode D₄.

A nonreactive resistor R₃ is coupled between the control electrode ofthe second transistor Q₂ and the first connection terminal of the input.This resistor can be used to further reduce the harmonic content of theinput current, since the converter cannot otherwise transmit any powerin the region of the zero crossing of the input voltage when On timesare too short.

Continuous operation of the circuit arrangement according to theinvention is used to limit the current amplitude of the current i₁ toi_(1,max) √{square root over (3)}*i_(g). This reduces the requirementsin terms of components, in particular for saturation of the inductanceL₁.

The switching frequency f in the circuit arrangement according to theinvention is f=1/(T₁+T₂). Since, according to equation (3), T₂ isdependent on the input voltage u_(g), the spectrum of the conducted,emitted noise during operation using the system voltage u_(e) issmoothed. The lowest frequency is reached at high input voltages u_(g).Since at high input voltages the highest currents i₁ in the inductanceL₁ need to be disconnected, the circuit can be dimensioned such that,below the step change in the evaluation curve, this frequency is 50 kHz.

According to equation (1), the capacitor C₁, together with thenonreactive resistor R₂, determines the time constant T₁. The capacitorC₁, however, has even further advantageous functions in the circuitarrangement according to the invention:

-   -   The capacitor C₁ makes it possible to rapidly deplete the base        of the transistor Q₂ at time t₂ by means of positive feedback in        the switching phase.    -   Conversely, at time t₁, the capacitor C₁ assists, likewise by        means of the effect of positive feedback, in switching the        transistor Q₂ on and thus in a “hard” turn-off of the transistor        Q₁. Depending on the dimensions, it may be necessary to protect        the base of the transistor Q₂ against overcurrent when the        capacitor C₁ is recharged, by means of two diodes D_(2a),        D_(2b), see FIG. 2, in parallel with the base/emitter path of        the transistor Q₂. The zener diode D_(2b) limits the negative        base/emitter voltage of the transistor Q₂. The time T₁ is thus        independent of component scatter and temperature behavior of the        breakdown voltage of the transistor Q₂.    -   The capacitor C₁ limits the edge steepness when the polarity of        the voltage across the inductance L₁ is reversed.

The transistor Q₂ advantageously clamps the gate of the transistor Q₁“hard” at zero volts. This is necessary for recharging the gatecapacitance of the transistor Q₁ rapidly and for causing the transistorQ₁ to turn off rapidly. In addition, the switching losses in thetransistor Q₁ can thus be kept low. Conversely, the transistor Q₁ isswitched on by means of the pull-up resistor R₁. This may take place“softly”, since the current i₁ in the inductance L₁ at this time mustfirst be built up starting from zero.

In order to protect the gate in this circuit against overvoltages, azener diode D₃, see FIG. 2, can be connected between the gate terminaland the reference potential for the transistor Q₁.

In one advantageous development of the invention, the pull-up resistorR₁ is connected to an internal low-voltage supply. The zener diode D₃may thus be dispensed with. Furthermore, this measure makes it possibleto dispense with the high voltage requirements for the resistor R₁.

FIG. 4 shows the time characteristic of the output voltage u_(z) of thecurrent i₁ and of the voltage u_(base) across the base of the transistorQ₂ over time using an experimental design for a circuit arrangementaccording to the invention. The voltage peaks in the characteristics forthe voltages u_(z) and u_(base) result from the recharge currents of thecapacitor C₁ and lead to losses in the transistor Q₂, as long as theyare not derived using optionally inserted diodes D_(2a) and D_(2b).

FIG. 5 shows the time characteristic of the input current i_(e) whendriving using a sinusoidal system voltage u_(e). In the region of thezero crossing of the system voltage u_(e), the voltage across theinductance L₁ no longer reaches the output voltage u_(z). Power transferis thus not possible in this region for a very short period of time.These current distortions result in a harmonic content which can betolerated depending on requirements. The additionally introduced thirdresistor R₃ between the base of the transistor Q₂ and the rectifiedinput voltage can be used to largely compensate for this effect.

FIG. 6 shows a further exemplary embodiment of the invention. Incontrast to FIG. 2, a second capacitor C2 is connected between thecontrol electrode and the reference electrode of the second switchingelement Q2. In addition, the reference electrode of the second switchingelement Q2 is connected to the reference potential via a fourth resistorR4. The second capacitor C2 eliminates one disadvantage which arisesowing to the multiple function of the first capacitor C1. Firstly, thevalue of the first capacitor C1 determines the On time T1 of the firstswitching element Q1, and secondly the first capacitor C1 represents thepositive feedback which maintains the oscillation of the entire circuitarrangement. In practice, changes in the voltage of several hundredvolts occur across the first capacitor C1. As well as the desired valuefor the first capacitor C1, undesirably high charge and dischargecurrents result which entail high component loads. According to theinvention, the second capacitor cancels out the multiple function of thefirst capacitor C1. The value for the second capacitor C2 is selectedsuch that it essentially determines the On time T1 of the firstswitching element Q1. The value for the first capacitor C1 can then beselected to be so small that only its positive feedback function ismaintained. The abovementioned charge and discharge currents can thus bereduced. The value for the fourth resistor R4 represents a furtherpossible way of influencing both the positive feedback function of thefirst capacitor C1 and the On time T1 of the first switching element Q1.Fine tuning is thus possible. The value for the fourth resistor R4 mayalso be zero, however.

In summary, the circuit arrangement according to the invention resultsin particular in the following advantages:

-   -   depletion, by virtue of the principle, of the transistors,        brought about by the positive feedback by means of the capacitor        C₁ when the transistor Q₁ turns off, makes possible low-loss        switching of high currents;    -   the capacitor C₁ or the capacitors C₁ and C₂ are responsible for        dimensioning of the time T₁ and at the same time cause the        transistor Q₁ to turn off in the zero crossing of the current i₁        in the inductance L₁;    -   the capacitor C₁ or the capacitors C₁ and C₂ make possible a        “soft” commutation of the current i₁ at time t₁;    -   the variation in the output voltage u_(z) as a result of a        variation in the load is partially, i.e. linearly instead of        quadratically, adjusted by the dependence of the time T₁ on the        output voltage u_(z).

1. A circuit arrangement for power factor correction having an input, towhich an input voltage (u_(g)) can be connected, the input comprising afirst and a second connection terminal; a first switching element (Q₁)having a control electrode, a reference electrode and a workingelectrode, the control electrode being coupled to a current source andthe reference electrode being coupled to a reference potential; aninductance (L₁), which is coupled between the working electrode of thefirst switching element (Q₁) and the first connection terminal of theinput; an output, at which an output voltage (u_(z)) can be provided,the output comprising a first and a second output terminal; a firstdiode (D₁), which is coupled between the working electrode of the firstswitching element (Q₁) and the first output terminal of the output; asecond switching element (Q₂) having a control electrode, a referenceelectrode and a working electrode, the reference electrode being coupledto the reference potential, and the working electrode being coupled tothe control electrode of the first switching element (Q₁); a firstcapacitor (C₁), which is coupled between the control electrode of thesecond switching element (Q₂) and the working electrode of the firstswitching element (Q₁); and a first nonreactive resistor (R₂), which iscoupled between the first connection terminal of the output and thecontrol electrode of the second switching element (Q₂).
 2. The circuitarrangement as claimed in claim 1, characterized in that the currentsource, to which the control electrode of the first switching element(Q₁) is coupled, is realized by a second nonreactive resistor (R₁) whichis coupled to the first connection terminal of the input.
 3. The circuitarrangement as claimed in claim 1, characterized in that the currentsource, to which the control electrode of the first switching element(Q₁) is coupled, is realized by a separate low-voltage source having ahigh impedance.
 4. The circuit arrangement as claimed in claim 1,characterized in that a first zener diode (D₄) is connected in parallelwith the first nonreactive resistor (R₂) such that it can be used tolimit the output voltage (u_(z)).
 5. The circuit arrangement as claimedin claim 1, characterized in that the first switching element (Q₁)comprises an nmos transistor, and/or the second switching element (Q₂)comprises an npn transistor.
 6. The circuit arrangement as claimed inclaim 1, characterized in that the first switching element (Q₁)comprises a pmos transistor, and/or the second switching element (Q₂)comprises a pnp transistor.
 7. The circuit arrangement as claimed inclaim 1, characterized in that the circuit arrangement is designed suchthat, during a zero crossing of the current (i₁) through the inductance(L₁), the first switching element (Q₁) opens.
 8. The circuit arrangementas claimed in claim 1, characterized in that a third nonreactiveresistor (R₃) is coupled between the control electrode of the secondswitching element (Q₂) and the first connection terminal of the input.9. The circuit arrangement as claimed in claim 1, characterized in thatthe series circuit comprising a second diode (D_(2a)) and a second zenerdiode (D_(2b)) is coupled between the control electrode and thereference electrode of the second switching element (Q₂) such that thesecond zener diode (D_(2b)) limits the voltage between the controlelectrode and the reference electrode of the second switching element(Q₂) in the reverse direction, and the second diode (D_(2a)) prevents ashort circuit of the control electrode of the second switching element(Q₂) with respect to its reference electrode by means of the secondzener diode (D_(2b)).
 10. The circuit arrangement as claimed in claim 1,characterized in that the control electrode of the first switchingelement (Q₁) and the working electrode of the second switching element(Q₂) are coupled to the reference potential by means of a third zenerdiode (D₃), the third zener diode (D₃) being arranged such that it canbe used to protect the control electrode of the first switching element(Q₁) against overvoltages.
 11. The circuit arrangement as claimed inclaim 1, characterized in that a second capacitor (C2) is connectedbetween the control electrode of the second switching element (Q₂) andthe reference electrode of the second switching element (Q₂), and thevalue for the second capacitor (C2) is so great that it can be used tosubstantially influence the On time (T1) of the first switching element(Q1).